#ifndef HI1823_CSR_SM_ADDR_DEFINE_H
#define HI1823_CSR_SM_ADDR_DEFINE_H

#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif /* * __cplusplus */

/* * smrt_csr base address */
#define CSR_SMRT_CSR_BASE_ADDR 0xa00

/* * SMRT_CSR address */
#define CSR_SMRT_VERSION_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x0)
#define CSR_SMXR_CFG1_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x4)
#define CSR_SMXR_CFG0_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x8)
#define CSR_SMXT_CFG_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0xC)
#define CSR_SMXR_TM_GRT01_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x10)
#define CSR_SMXR_TM_GRT23_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x14)
#define CSR_SMRT_INT_VECTOR_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x18)
#define CSR_SMRT_INT_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x1C)
#define CSR_SMRT_INT_MASK_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x20)
#define CSR_SMXR_REQ_MEM_CRT_ERR_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x24)
#define CSR_SMXR_REQ_MEM_UNCRT_ERR_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x28)
#define CSR_SMXR_MISS_SOP_EOP_ERR_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x2C)
#define CSR_SMXR_INDRECT_CTRL_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x30)
#define CSR_SMXR_INDRECT_TIMEOUT_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x34)
#define CSR_SMXR_INDRECT_DATA_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x38)
#define CSR_SMXT_CAP_CFG_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x3C)
#define CSR_SMXT_CAP_FIELD_CFG_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x40)
#define CSR_SMXT_CNT_CFG0_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x44)
#define CSR_SMXT_CNT_CFG1_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x48)
#define CSR_SMXT_CNT0_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x4C)
#define CSR_SMXT_CNT1_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x50)
#define CSR_SMXT_CNT2_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x54)
#define CSR_SMXT_CNT3_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x58)
#define CSR_SMXT_CRDT_CNT_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x5C)
#define CSR_SMXT_FIFO_DEPTH0_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x60)
#define CSR_SMXT_FIFO_DEPTH1_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x68)
#define CSR_TL0_Q_DEP_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x6C)
#define CSR_TL1_Q_DEP_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x70)
#define CSR_RQST_Q_DEP_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x74)
#define CSR_RSP_Q_DEP_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x78)
#define CSR_RQST_CRDT_CNT_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x7C)
#define CSR_RESP_CRDT_CNT_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x80)
#define CSR_SMXR_CNT0_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x84)
#define CSR_SMXR_CNT1_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x88)
#define CSR_SMXR_CNT2_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x8C)
#define CSR_SMXR_CNT3_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x90)
#define CSR_SMXT_CTP_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x94)
/* * smir_csr base address */
#define CSR_SMIR_CSR_BASE_ADDR 0x100

/* * SMIR_CSR address */
#define CSR_SMIR_VERSION_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x0)
#define CSR_SMIR_CFG_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x4)
#define CSR_SMIR_HASH_SEED0_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x8)
#define CSR_SMIR_HASH_SEED1_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0xC)
#define CSR_SMIR_INT_VECTOR_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x10)
#define CSR_SMIR_INT_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x14)
#define CSR_SMIR_INT_MASK_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x18)
#define CSR_SMIR_ERR_SPEC_TH_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x1C)
#define CSR_SMIR_REQ_MSG_ERR_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x20)
#define CSR_SMIR_RESP_MSG_ERR_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x24)
#define CSR_SMIR_MEM_ECC_CRT_ERR_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x28)
#define CSR_SMIR_MEM_ECC_UNCRT_ERR_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x2C)
#define CSR_SMIR_INDRECT_CTRL_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x30)
#define CSR_SMIR_INDRECT_TIMEOUT_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x34)
#define CSR_SMIR_INDRECT_DATA_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x38)
#define CSR_SMIR_CAP0_CFG_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x3C)
#define CSR_SMIR_CAP1_CFG_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x40)
#define CSR_SMIR_CAP2_CFG_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x44)
#define CSR_SMIR_CAP3_CFG_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x48)
#define CSR_SMIR_CAP4_CFG_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x4C)
#define CSR_SMIR_CAP6_CFG_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x50)
#define CSR_SMIR_EN_CNT_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x54)
#define CSR_SMIR_CNT0_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x58)
#define CSR_SMIR_CNT1_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x5C)
#define CSR_SMIR_CNT2_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x60)
#define CSR_SMIR_CRDT_CNT_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x64)
#define CSR_SMIR_CAP_FLIT0_DATA0_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x68)
#define CSR_SMIR_CAP_FLIT0_DATA1_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x70)
#define CSR_SMIR_CAP_FLIT1_DATA0_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x78)
#define CSR_SMIR_CAP_FLIT1_DATA1_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x80)
#define CSR_SMIR_CAP_FLIT2_DATA0_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x88)
#define CSR_SMIR_CAP_FLIT2_DATA1_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x90)
#define CSR_SMIR_CAP_FLIT3_DATA0_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x98)
#define CSR_SMIR_CAP_FLIT3_DATA1_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0xA0)
#define CSR_SMIR_CAP_FLIT4_DATA0_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0xA8)
#define CSR_SMIR_CAP_FLIT4_DATA1_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0xB0)
#define CSR_SMIR_CAP_FLIT5_DATA0_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0xB8)
#define CSR_SMIR_CAP_FLIT5_DATA1_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0xC0)
#define CSR_SMIR_CAP_FLIT0_DATA2_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0xC8)
#define CSR_SMIR_CAP_FLIT1_DATA2_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0xCC)
#define CSR_SMIR_CAP_FLIT2_DATA2_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0xD0)
#define CSR_SMIR_CAP_FLIT3_DATA2_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0xD4)
#define CSR_SMIR_CAP_FLIT4_DATA2_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0xD8)
#define CSR_SMIR_CAP_FLIT5_DATA2_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0xDC)
/* * smeg0_abuf0_csr base address */
#define CSR_SMEG0_ABUF0_CSR_BASE_ADDR 0x200

/* * SMEG0_ABUF0_CSR address */
#define CSR_SMEG0_ABUF0_VERSION_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x0)
#define CSR_SM_ABUF_TH_GRW_WM_0_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x4)
#define CSR_SM_ABUF_TH_GRW_WM_1_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x8)
#define CSR_SM_ABUF_TH_GRW_WM_2_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xC)
#define CSR_SM_ABUF_TH_GRW_WM_3_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x10)
#define CSR_SM_ABUF_TH_GRW_WM_4_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x14)
#define CSR_SM_ABUF_TH_GRW_WM_5_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x18)
#define CSR_SM_ABUF_TH_GRW_WM_6_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x1C)
#define CSR_SM_ABUF_TH_SHK_WM_0_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x20)
#define CSR_SM_ABUF_TH_SHK_WM_1_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x24)
#define CSR_SM_ABUF_TH_SHK_WM_2_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x28)
#define CSR_SM_ABUF_TH_SHK_WM_3_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x2C)
#define CSR_SM_ABUF_TH_SHK_WM_4_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x30)
#define CSR_SM_ABUF_TH_SHK_WM_5_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x34)
#define CSR_SM_ABUF_TH_SHK_WM_6_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x38)
#define CSR_SM_ABUF_FLRC_ATTR_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x3C)
#define CSR_SM_ABUF_FLRC_NUM_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x40)
#define CSR_SM_ABUF_FLRC_BOUND_U_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x44)
#define CSR_SM_ABUF_FLRC_BOUND_L_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x48)
#define CSR_SM_ABUF_PF_LIFO_CLR_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x4C)
#define CSR_SM_ABUF_MEM_CFG_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x50)
#define CSR_SM_ABUF_INT_VECTOR_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x54)
#define CSR_SM_ABUF_INT_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x58)
#define CSR_SM_ABUF_INT_MASK_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x5C)
#define CSR_SM_ABUF_PBERR_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x60)
#define CSR_SM_ABUF_FL_UFLOW_ERR_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x64)
#define CSR_SM_ABUF_FL_OFLOW_ERR_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x68)
#define CSR_SM_ABUF_FL_TAIL_MISS_ERR_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x6C)
#define CSR_SMEG0_ABUF_INDRECT_CTRL_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x70)
#define CSR_SMEG0_ABUF_INDRECT_TIMEOUT_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x74)
#define CSR_SMEG0_ABUF_INDRECT_DATA_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x78)
#define CSR_SM_ABUF_DIS_ALLOC_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x7C)
#define CSR_SM_ABUF_DIS_DE_ALLOC_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x80)
#define CSR_SM_ABUF_FLRC_ST_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x84)
#define CSR_SM_ABUF_EMPTY_FL_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x88)
#define CSR_SM_ABUF_FULL_FL_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x8C)
#define CSR_SM_ABUF_ST_WM_GROW_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x90)
#define CSR_SM_ABUF_ST_WM_SHRINK_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x94)
#define CSR_SM_ABUF_CNT_SEL0_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x98)
#define CSR_SM_ABUF_CNT_SEL1_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x9C)
#define CSR_SM_ABUF_COUNTER0_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xA0)
#define CSR_SM_ABUF_COUNTER1_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xA4)
#define CSR_SM_ABUF_COUNTER2_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xA8)
#define CSR_SM_ABUF_COUNTER3_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xAC)
#define CSR_SM_ABUF_COUNTER4_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xB0)
#define CSR_SM_ABUF_COUNTER5_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xB4)
#define CSR_SM_ABUF_PFETCH_FLAG_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xB8)
#define CSR_SM_ABUF_IREQ_LIST_STA_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xBC)
#define CSR_SM_ABUF_TAIL_MISS0_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xC0)
#define CSR_SM_ABUF_TAIL_MISS1_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xC8)
#define CSR_SM_ABUF_CNT_LIFO_PFETCH_0_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xD0)
#define CSR_SM_ABUF_CNT_LIFO_PFETCH_1_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xD8)
#define CSR_SM_ABUF_CNT_LIFO_PFETCH_2_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xE0)
#define CSR_SM_ABUF_ECC_CFG_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xE4)
#define CSR_SM_ABUF_ECC_1B_ERR_INT_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xE8)
#define CSR_SM_ABUF_ECC_2B_ERR_INT_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xEC)
/* * smeg0_aget_csr base address */
#define CSR_SMEG0_AGET_CSR_BASE_ADDR 0x300

/* * SMEG0_AGET_CSR address */
#define CSR_SMEG0_AGET_VERSION_ADDR (CSR_SMEG0_AGET_CSR_BASE_ADDR + 0x0)
#define CSR_SMEG0_AGET_CFG_ADDR (CSR_SMEG0_AGET_CSR_BASE_ADDR + 0x4)
#define CSR_SMEG0_AGET_INT_VECTOR_ADDR (CSR_SMEG0_AGET_CSR_BASE_ADDR + 0x8)
#define CSR_SMEG0_AGET_INT_ADDR (CSR_SMEG0_AGET_CSR_BASE_ADDR + 0xC)
#define CSR_SMEG0_AGET_INT_MASK_ADDR (CSR_SMEG0_AGET_CSR_BASE_ADDR + 0x10)
#define CSR_SMEG0_AGET_MEM_PRTY_ERR_ADDR (CSR_SMEG0_AGET_CSR_BASE_ADDR + 0x14)
#define CSR_SMEG0_AGET_BOUNDARY_ERR_ADDR (CSR_SMEG0_AGET_CSR_BASE_ADDR + 0x18)
#define CSR_SMEG0_AGET_INDRECT_CTRL_ADDR (CSR_SMEG0_AGET_CSR_BASE_ADDR + 0x1C)
#define CSR_SMEG0_AGET_INDRECT_TIMEOUT_ADDR (CSR_SMEG0_AGET_CSR_BASE_ADDR + 0x20)
#define CSR_SMEG0_AGET_INDRECT_DATA_ADDR (CSR_SMEG0_AGET_CSR_BASE_ADDR + 0x24)
#define CSR_SMEG_CORE_MEM_INIT_ADDR (CSR_SMEG0_AGET_CSR_BASE_ADDR + 0x28)
#define CSR_SMEG0_CNT0_ADDR (CSR_SMEG0_AGET_CSR_BASE_ADDR + 0x2C)
#define CSR_SMEG0_CNT1_ADDR (CSR_SMEG0_AGET_CSR_BASE_ADDR + 0x30)
/* * smeg0_lu_csr base address */
#define CSR_SMEG0_LU_CSR_BASE_ADDR 0x400

/* * SMEG0_LU_CSR address */
#define CSR_SMEG0_LU_VERSION_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x0)
#define CSR_SMEG0_LU_CHK_ENABLE_CFG_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x4)
#define CSR_SMEG0_LU_INT_VECTOR_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x8)
#define CSR_SMEG0_LU_INT_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0xC)
#define CSR_SMEG0_LU_INT_MASK_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x10)
#define CSR_SMEG0_LU_PIPE0_MEM_ECC_CRT_ERR_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x14)
#define CSR_SMEG0_LU_PIPE0_MEM_ECC_UNCRT_ERR_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x18)
#define CSR_SMEG0_LU_PIPE1_MEM_ECC_CRT_ERR_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x1C)
#define CSR_SMEG0_LU_PIPE1_MEM_ECC_UNCRT_ERR_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x20)
#define CSR_SMEG0_LU_FLITFIFO_MEM_ECC_CRT_ERR_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x24)
#define CSR_SMEG0_LU_FLITFIFO_MEM_ECC_UNCRT_ERR_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x28)
#define CSR_SMEG0_LU_SW_ERR_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x2C)
#define CSR_SMEG0_LU_INDRECT_CTRL_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x30)
#define CSR_SMEG0_LU_INDRECT_TIMEOUT_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x34)
#define CSR_SMEG0_LU_INDRECT_DATA_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x38)
#define CSR_SMEG0_LU_ERR_INJ_CFG_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x3C)
#define CSR_SMEG0_LU_CNT_CFG_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x40)
#define CSR_SMEG0_LU_CNT0_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x44)
#define CSR_SMEG0_LU_CNT1_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x48)
#define CSR_SMEG0_LU_CNT2_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x4C)
#define CSR_SMEG0_LU_CNT3_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x50)
#define CSR_SMEG0_LU_CTP_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x54)
/* * smeg1_csr base address */
#define CSR_SMEG1_CSR_BASE_ADDR 0x500

/* * SMEG1_CSR address */
#define CSR_SMEG1_VERSION_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x0)
#define CSR_SMEG1_CFG0_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x4)
#define CSR_SMEG1_CFG1_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x8)
#define CSR_SMEG1_RUNAWAY_CFG_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0xC)
#define CSR_SMEG1_THREAD_ENABLE_CFG_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x10)
#define CSR_SMEG1_TM_TS_FAST2_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x14)
#define CSR_SMEG1_TM_TS_FAST3_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x18)
#define CSR_SMEG1_TM_TS_SLOW0_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x1C)
#define CSR_SMEG1_TM_TS_SLOW1_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x20)
#define CSR_SMEG1_TM_TMT_CFG7_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x24)
#define CSR_SMEG1_TM_TMT_CFG6_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x28)
#define CSR_SMEG1_TM_TMT_CFG5_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x2C)
#define CSR_SMEG1_TM_TMT_CFG4_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x30)
#define CSR_SMEG1_TM_TMT_CFG3_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x34)
#define CSR_SMEG1_TM_TMT_CFG2_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x38)
#define CSR_SMEG1_TM_TMT_CFG1_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x3C)
#define CSR_SMEG1_TM_TMT_CFG0_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x40)
#define CSR_SMEG1_INT_VECTOR_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x44)
#define CSR_SMEG1_INT_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x48)
#define CSR_SMEG1_INT_MASK_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x4C)
#define CSR_SMEG1_ENGINE_SW_ERR_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x50)
#define CSR_SMEG1_ERR0_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x54)
#define CSR_SMEG1_ERR0_MASK_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x58)
#define CSR_SMEG1_ERR1_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x5C)
#define CSR_SMEG1_ERR1_MASK_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x60)
#define CSR_SMEG1_INDRECT_CTRL_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x64)
#define CSR_SMEG1_INDRECT_TIMEOUT_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x68)
#define CSR_SMEG1_INDRECT_DATA_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x6C)
#define CSR_SMEG1_CNT_CFG_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x70)
#define CSR_SMEG1_CNT_MATCH_ID_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x74)
#define CSR_SMEG1_CNT0_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x78)
#define CSR_SMEG1_CNT1_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x80)
#define CSR_SMEG1_CNT2_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x88)
#define CSR_SMEG1_CNT3_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x90)
#define CSR_SMEG1_TCD_CTP_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x98)
#define CSR_SMEG1_RUNAWAY_THD_CTP_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x9C)
#define CSR_SMEG1_CTP0_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0xA0)
#define CSR_SMEG1_CTP1_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0xA8)
#define CSR_SMEG1_CTP2_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0xB0)
#define CSR_SMEG1_TMT_EXT_CFG_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0xB4)
#define CSR_SMEG1_MEM_ECC_ERR_CTP_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0xB8)
#define CSR_SMMC_CACHE_RESOURCE_CTP_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0xBC)
#define CSR_SMEG1_SYNC_API_CFG_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0xC0)
#define CSR_SMEG1_CUR_TIMESTAMP_US_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0xC8)
/* * smit_csr base address */
#define CSR_SMIT_CSR_BASE_ADDR 0x600

/* * SMIT_CSR address */
#define CSR_SMIT_VERSION_ADDR (CSR_SMIT_CSR_BASE_ADDR + 0x0)
#define CSR_SMIT_CFG_ADDR (CSR_SMIT_CSR_BASE_ADDR + 0x4)
#define CSR_SMIT_INT_VECTOR_ADDR (CSR_SMIT_CSR_BASE_ADDR + 0x8)
#define CSR_SMIT_INT_ADDR (CSR_SMIT_CSR_BASE_ADDR + 0xC)
#define CSR_SMIT_INT_MASK_ADDR (CSR_SMIT_CSR_BASE_ADDR + 0x10)
#define CSR_SMIT_ERR_PRTY_ADDR (CSR_SMIT_CSR_BASE_ADDR + 0x14)
#define CSR_SMIT_MEM_ECC_CRT_ERR_ADDR (CSR_SMIT_CSR_BASE_ADDR + 0x18)
#define CSR_SMIT_MEM_ECC_UNCRT_ERR_ADDR (CSR_SMIT_CSR_BASE_ADDR + 0x1C)
#define CSR_SMIT_INDRECT_CTRL_ADDR (CSR_SMIT_CSR_BASE_ADDR + 0x20)
#define CSR_SMIT_INDRECT_TIMEOUT_ADDR (CSR_SMIT_CSR_BASE_ADDR + 0x24)
#define CSR_SMIT_INDRECT_DATA_ADDR (CSR_SMIT_CSR_BASE_ADDR + 0x28)
/* * smlc_csr base address */
#define CSR_SMLC_CSR_BASE_ADDR 0x700

/* * SMLC_CSR address */
#define CSR_SMLC_VERSION_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x0)
#define CSR_SMLC_CFG0_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x4)
#define CSR_SMLC_CFG1_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x8)
#define CSR_SMLC_CFG2_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0xC)
#define CSR_SMLC_INT_VECTOR_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x10)
#define CSR_SMLC_INT_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x14)
#define CSR_SMLC_INT_MASK_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x18)
#define CSR_SMLC_SRF_OV_ERR_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x1C)
#define CSR_SMLC_ECC_ERR_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x24)
#define CSR_SMLC_ECC_ERRPR_MASK_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x28)
#define CSR_SMLC_INDRECT_CTRL_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x2C)
#define CSR_SMLC_INDRECT_TIMEOUT_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x30)
#define CSR_SMLC_INDRECT_DATA_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x34)
#define CSR_SMLC_CNT0_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x38)
#define CSR_SMLC_CNT1_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x40)
#define CSR_SMLC_CNT2_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x48)
#define CSR_SMLC_CNT3_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x50)
#define CSR_SMLC_CNT_CFG0_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x58)
#define CSR_SMLC_CNT_CFG1_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x5C)
#define CSR_SMLC_CREDIT_CTP_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x60)
#define CSR_SMLC_FIFO_DEPTH_CTP_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x64)
#define CSR_SMLC_ECC_ERR_CTP_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x68)
/* * smmc_f_csr base address */
#define CSR_SMMC_F_CSR_BASE_ADDR 0x800

/* * SMMC_F_CSR address */
#define CSR_SMMC_F_VERSION_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x0)
#define CSR_SMMC_F_MC_CFG_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x4)
#define CSR_SMMC_F_MC_CFG1_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x8)
#define CSR_SMMC_HASH_SEED0_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xC)
#define CSR_SMMC_HASH_SEED1_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x10)
#define CSR_SMMC_F_CFG_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x14)
#define CSR_SMMC_F_MC_INIT_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x18)
#define CSR_SMMC_F_MC_RF_TIMEOUT_INTERVAL_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x1C)
#define CSR_SMMC_F_INT_VECTOR_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x20)
#define CSR_SMMC_F_INT_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x24)
#define CSR_SMMC_F_INT_MASK_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x28)
#define CSR_SMMC_F_MC_CACHE_ERR_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x2C)
#define CSR_SMMC_F_MC_CACHE_MASK_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x30)
#define CSR_SMMC_F_MC_CACHE_ERR_INFO_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x34)
#define CSR_SMMC_F_BUFFER_ERR_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x38)
#define CSR_SMMC_F_BUFFER_MASK_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x3C)
#define CSR_SMMC_F_BUFFER_ERR_INFO_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x40)
#define CSR_SMMC_F_MC_RF_RTN_ERR_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x44)
#define CSR_SMMC_F_MC_RF_TIMEOUT_ERR_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x48)
#define CSR_SMMC_F_MC_MULTI_HIT_ERR_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x4C)
#define CSR_SMMC_F_VC_CACHE_ERR_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x50)
#define CSR_SMMC_F_VC_CACHE_MASK_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x54)
#define CSR_SMMC_F_VC_CACHE_ERR_INFO_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x58)
#define CSR_SMMC_F_INDRECT_CTRL_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x5C)
#define CSR_SMMC_F_INDRECT_TIMEOUT_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x60)
#define CSR_SMMC_F_INDRECT_DATA_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x64)
#define CSR_SMMC_F_MC_CNT_ENB_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x68)
#define CSR_SMMC_F_MC_CNT_EVENT_SEL_ENB_GRP0_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x6C)
#define CSR_SMMC_F_MC_CNT_EVENT_SEL_ENB_GRP1_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x70)
#define CSR_SMMC_F_MC_CNT_EVENT_SEL0_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x74)
#define CSR_SMMC_F_MC_CNT_EVENT_SEL1_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x78)
#define CSR_SMMC_F_MC_CNT_EVENT_SEL2_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x7C)
#define CSR_SMMC_F_MC_CNT_EVENT_SEL3_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x80)
#define CSR_SMMC_F_MC_CNT_EVENT_SEL4_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x84)
#define CSR_SMMC_F_MC_CNT_EVENT_SEL5_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x88)
#define CSR_SMMC_F_MC_CNT_EVENT_SEL6_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x8C)
#define CSR_SMMC_F_MC_CNT_EVENT_SEL7_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x90)
#define CSR_SMMC_F_MC_STATUS_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x94)
#define CSR_SMMC_F_MC_CNT0_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x98)
#define CSR_SMMC_F_MC_CNT1_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xA0)
#define CSR_SMMC_F_MC_CNT2_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xA8)
#define CSR_SMMC_F_MC_CNT3_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xB0)
#define CSR_SMMC_F_MC_CNT4_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xB8)
#define CSR_SMMC_F_MC_CNT5_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xC0)
#define CSR_SMMC_F_MC_CNT6_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xC8)
#define CSR_SMMC_F_MC_CNT7_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xD0)
#define CSR_SMMC_F_VC_FIFO_DEPTH0_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xD8)
#define CSR_SMMC_F_VC_FIFO_DEPTH1_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xDC)
#define CSR_SMMC_F_MC_FIFO1_DEPTH_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xE0)
#define CSR_SMMC_F_MC_FIFO2_DEPTH_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xE4)
#define CSR_SMMC_F_ERR_INJ_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xE8)
#define CSR_SMMC_F_GPA_TRANS_ERR_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xEC)
#define CSR_SMMC_F_QU_INTF_CNT_CFG_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xF0)
#define CSR_SMMC_F_QU_INTF_RX_CNT_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xF4)
#define CSR_SMMC_F_QU_INTF_TX_CNT_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xF8)
#define CSR_SMMC_F_MC_CFG2_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xFC)
/* * smmc_l_csr base address */
#define CSR_SMMC_L_CSR_BASE_ADDR 0x900

/* * SMMC_L_CSR address */
#define CSR_SMMC_L_VERSION_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x0)
#define CSR_SMMC_L_CFG_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x4)
#define CSR_SMMC_L_STAT_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x8)
#define CSR_SMMC_L_INT_VECTOR_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0xC)
#define CSR_SMMC_L_INT_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x10)
#define CSR_SMMC_L_INT_MASK_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x14)
#define CSR_SMMC_L_MEM_ERR_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x18)
#define CSR_SMMC_L_MEM_ERR_MASK_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x1C)
#define CSR_SMMC_L_MEM_ERR_INFO_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x20)
#define CSR_SMMC_L_INDRECT_CTRL_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x24)
#define CSR_SMMC_L_INDRECT_TIMEOUT_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x28)
#define CSR_SMMC_L_INDRECT_DATA_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x2C)
#define CSR_SMMC_L_CNT_CFG_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x30)
#define CSR_SMMC_L_CNT_MATCH_BANK_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x34)
#define CSR_SMMC_L_CNT_MATCH_INSTANCE_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x38)
#define CSR_SMMC_L_CNT0_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x3C)
#define CSR_SMMC_L_CNT1_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x40)
#define CSR_SMMC_L_CNT2_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x44)
#define CSR_SMMC_L_CNT3_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x48)
#define CSR_SMMC_L_BANK_QUEUE_DEPTH_CTP0_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x4C)
#define CSR_SMMC_L_BANK_QUEUE_DEPTH_CTP1_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x50)
#define CSR_SMMC_L_ECC_INJ_CFG_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x54)
#define CSR_SMMC_L_PG_CFG_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x58)
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* * __cplusplus */

#endif /* * HI1823_CSR_SM_ADDR_DEFINE_H */
